The predominant form of flash is NAND flash, and since the early 2000s, its cost has been tumbling. In 2005, it was more expensive than DRAM, per gigabyte capacity. Now, it is about 30 times cheaper. This has been the result of advances in flash technology, alongside heavy investment in manufacturing that have driven up supply to match exploding demand.

In 2016, however, NAND entered a period of shortages, and prices began rising. The undersupply is widely expected to end next year or sooner, and its cause is the current transition of the NAND flash manufacturing industry from 2-D to 3-D chips. The reward for the disruption is a restoration of the technology curve, and a promise that, once completed, prices will return to a downward trajectory for multiple years, and generations of chips. While a 3-D multilayer chip architecture is the major technical element behind that promise, it is not the only one.

In a separate report about rising NAND flash prices, 451 Research concluded that NAND prices are unlikely to return to their historically very steep rates of descent, because of the growing size of the capital spending involved in manufacturing flash. But that does not mean the descent rate won't still be significant, or will not be prolonged, because flash chipmakers see a long technology road map ahead.

3-D: bigger, better, cheaper chips

The move away from 2-D flash chips began in 2013, when Samsung became the first supplier to produce 3-D chips, with multiple, stacked layers of memory cells. By adding a vertical dimension to the chips, this architecture transforms the ability to scale the capacity of NAND flash chips, and renews the technology and price curves.

Before the move to 3-D chips, a major reason for the rapid descent in flash chip prices was the reduction in chip-making process or geometry sizes within 2-D chips. The smaller the process size, the more memory cells can be packed into a chip, and hence the lower the price per unit of storage capacity. However, the process size cannot be reduced to below about 10-15 nanometers. As chipmakers began to draw near this dead end, they switched to another route that would allow cost reductions to continue, namely 3-D chips.

Although the 3-D architecture forced chipmakers to return to larger process sizes, that negative effect has been more than offset by the presence of multiple layers of memory cells. Initially, it was not clear how many layers could be stacked on top of each other, but over the last four years, the number has been increasing rapidly.

The first 3-D chips shipped with 24 layers. Now, 64-layer chips are entering volume production, and 96-layer chips are promised for 2018. While manufacturers are not saying how many layers will come after that, they are saying that there are multiple generations of chips ahead, and are implying that there will be more layers.

Alongside the increased total number of memory cells, the 3-D architecture delivers other benefits, including the ability to pack more data bits into each cell. Samsung says its 64-layer chips drive a 30% 'productivity gain,' use 30% less energy in operation, and are 20% more reliable than its previous 48-layer chips.

The 64-layer Samsung chips are 256Gb devices. The 96-layer chips that the company says will enter production next year will be four times larger in terms of capacity, at 1TB. They will also be the fifth generation of Samsung's 3-D NAND flash architecture, which the Korean giant brands as V-NAND. Samsung says V-NAND will be developed for at least 10 generations. With new generations emerging about once a year, we assume that means about another five years of V-NAND development or more.

Western Digital has also promised to put 96-layer chips into volume production next year. Although those chips will begin life as 256Gb devices, Western Digital says they will be developed into 1Tb devices. They were jointly developed by Western Digital's SanDisk division and Toshiba (and are therefore at the heart of a legal battle between Western Digital and Toshiba over the latter's planned sale of its flash chip-making business).

Micron is now sending samples of 512Gb, 64-layer NAND flash chips to customers, and says its progression to 96-layer chips will be smooth. Echoing Samsung's confidence, Micron says it also sees no limits for its BICS architecture for several generations yet.

Separately to layer counts, Micron has taken a technical lead in another area, by developing CMOS circuits that are located directly underneath the layers of flash memory cells, reducing the overall size of the chips by 20%. That makes the chips cheaper by allowing more of them to be produced from a single 300mm wafer, and boosts their performance, according to Micron. One of Micron's rivals has already said it will develop the same architecture.

More bits per cell: TLC

While NAND flash chipmakers have been packing more memory cells into each memory chip, they have also been packing more bits of data into each cell, which also helped significantly reduce costs per unit of storage capacity. About 10 years ago, the first NAND flash chips used in the datacenters stored one bit per memory cell, and were known as single-level cell (SLC) devices .

Around 2013, datacenter flash drives began using flash chips that store two bits per memory cell, known as multilevel cell (MLC) chips. Despite the doubling of storage capacity, that did not translate into an overnight halving of the per-gigabyte street price of enterprise flash drives, but it did make a significant contribution to price reductions.

Triple-level cell (TLC) flash stores three bits per memory cell, and was used in consumer devices long before it was used in datacenter products. That was because increasing the number of bits stored in each cell also reduces performance and write-life, which was acceptable for consumer devices, but not for enterprise-grade systems.

However, 3-D chips carry a bonus in that the physical properties of the cells are superior to those of 2-D chips, giving TLC sufficient life and performance to suit datacenter usage when it is implemented in 3-D chips. TLC 3-D chips began entering datacenter devices about 18 months ago, and TLC on 3-D chips is now widely expected to fully replace MLC on 2-D chips as the dominant form of datacenter flash.

Even more bits per cell: QLC

QLC, or four bits per cell, is the next frontier for datacenter flash, and multiple flash chipmakers are now approaching it. Toshiba has cited a third-party forecast that QLC will be 19% cheaper than TLC, while Micron has claimed that QLC will begin to challenge high-capacity 7.2K disk next year, at costs of roughly $0.03 to $0.04 per gigabyte.

But the transition from TLC to QLC may be far slower than the move from MLC to TLC, because there are diminishing returns when increasing the number of bits stored in each memory cell. The labels SLC, MLC, TLC and QLC are misnomers, because they actually refer to bit count, not voltage levels. For example, SLC stores one bit per cell, but uses two voltage levels. MLC stores two bits per cell, and uses four voltage levels, and TLC stores three bits using eight voltage levels.

From TLC to QLC, the bit count doubles again to 16. The need to distinguish between so many voltage levels significantly reduces both life and performance, in return for which QLC gives only a 33% increase in capacity.

One very large storage and server maker has told 451 Research that it will use QLC flash (in drives made by third parties), but that TLC will dominate enterprise usage in terms of capacity until about 2025. That supplier plans to use mixed tiers of TLC and QLC in its all-flash storage systems, because it expects second-generation QLC to be 30-40% cheaper than TLC. It also disagrees with Micron, and says QLC will not significantly displace nearline disk.

Western Digital has said that its SanDisk subsidiary has successfully developed QLC 3-D flash chips, including 96-layer devices. The drive-making giant says it already enjoyed commercial success selling QLC on 2-D chips, and we assume that has been into non-datacenter applications. It expects to productize QLC on 3-D flash across multiple applications, and although it did not say what those would be, we expect they will include datacenter usage.

Micron says it is confident that much of the performance and write-life gap between QLC and TLC can be narrowed, and that would probably be done using the same digital signal processing and other techniques that helped narrow the gap between MLC and SLC, when both were based on 2-D flash. However, QLC will still be slower, and suffer a shorter write-life than TLC. Clearly it will suit read-intensive applications better than write-intensive applications.

Micron has said that hyperscalers want the high-capacity flash drives that would be possible with QLC, and that ultimately QLC flash drives will be 10 times the capacity of disk drives. Pure Storage told 451 Research that in the short term, it doesn't expect to be using QLC flash due to its limited write-life, but expects to see QLC being use in hyperscale operations for archiving and backup.

Tim Stammers
Senior Analyst, Storage

Tim Stammers is a Senior Analyst at 451 Research, where he covers flash- and disk-based primary storage.

Jean Atelsek
Analyst, Digital Economics

Jean Atelsek is an analyst for 451 Research’s Digital Economics Unit, focusing on cloud pricing in the US and Europe.

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